Description: 这是一个用MAX+PLUSII开发FPGA（1K30器件）开发的李沙育图形发生器（硬件描述语言部分）。-This is a development with MAX PLUSII FPGA (1K30 device) developed Lissajous Pattern Generator (hardware description language). Platform: |
Size: 791509 |
Author:孔玉 |
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Description: 伪随机图案发生器设计实例，也是可以拿来用的，扩频和跳频通信有用-pseudo-random pattern generator design examples, and can be used with the frequency hopping spread spectrum communication and useful Platform: |
Size: 4554 |
Author:sunny_girl |
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Description: Uniform Generator
Computer simulations often require random numbers. One way to generate pseudo-random numbers is via a function of the form
where `` " is the modulus operator.
Such a function will generate pseudo-random numbers (seed) between 0 and MOD-1. One problem with functions of this form is that they will always generate the same pattern over and over. In order to minimize this effect, selecting the STEP and MOD values carefully can result in a uniform distribution of all values between (and including) 0 and MOD-1.
For example, if STEP = 3 and MOD = 5, the function will generate the series of pseudo-random numbers 0, 3, 1, 4, 2 in a repeating cycle. In this example, all of the numbers between and including 0 and MOD-1 will be generated every MOD iterations of the function. Note that by the nature of the function to generate the same seed(x+1) every time seed(x) occurs means that if a function will generate all the numbers between 0 and MOD-1, it will generate pseudo-random numbers uniformly with every MOD iterations.
If STEP = 15 and MOD = 20, the function generates the series 0, 15, 10, 5 (or any other repeating series if the initial seed is other than 0). This is a poor selection of STEP and MOD because no initial seed will generate all of the numbers from 0 and MOD-1.
Your program will determine if choices of STEP and MOD will generate a uniform distribution of pseudo-random numbers.
Input
Each line of input will contain a pair of integers for STEP and MOD in that order ( ).
Output
For each line of input, your program should print the STEP value right- justified in columns 1 through 10, the MOD value right-justified in columns 11 through 20 and either ``Good Choice" or ``Bad Choice" left-justified starting in column 25. The ``Good Choice" message should be printed when the selection of STEP and MOD will generate all the numbers between and including 0 and MOD-1 when MOD numbers are generated. Otherwise, your program should print the message ``Bad Choice". After each output test set, your program should print exactly one blank line.
Sample Input
3 5
15 20
63923 99999
Sample Output
3 5 Good Choice
15 20 Bad Choice
63923 99999 Good Choice
Platform: |
Size: 360 |
Author:samurai1x4kyo@126.com |
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Description: 这是一个用MAX+PLUSII开发FPGA（1K30器件）开发的李沙育图形发生器（硬件描述语言部分）。-This is a development with MAX PLUSII FPGA (1K30 device) developed Lissajous Pattern Generator (hardware description language). Platform: |
Size: 791552 |
Author:孔玉 |
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Description: A fast lexical analyser generator. It is a tool for generating programs that perform pattern-matching on text. There are many applications for Flex, including writing compilers in conjunction with GNU Bison Platform: |
Size: 64512 |
Author:qkw |
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Description: 伪随机图案发生器设计实例，也是可以拿来用的，扩频和跳频通信有用-pseudo-random pattern generator design examples, and can be used with the frequency hopping spread spectrum communication and useful Platform: |
Size: 4096 |
Author:sunny_girl |
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Description: 伪随机图案发生器的Quartus源程序，CDMA通信的学习中用硬件语言实现伪随机码。-Pseudo-random pattern generator Quartus source, CDMA communications hardware used to study the language to achieve pseudo-random code. Platform: |
Size: 4096 |
Author:w |
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Description: Proteus VSM Oscilloscope, Logic Analyser, Function Generator, Pattern Generator, Counter Timer and Virtual Terminal as well as simple voltmeters and ammeters.-Proteus VSM Oscilloscope, Logic Analyser, Function Generator, Pattern Generator, Counter Timer and Virtual Terminal as well as simple voltmeters and ammeters. Platform: |
Size: 19456 |
Author:songemi |
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Description: 前束范式生成器，数理逻辑的一个辅助程序，可以给出任意谓词公式的前束范式。主要采用二叉树方式实现-Before the beam pattern generator, an auxiliary mathematical logic program predicate formulas can be given before any beam pattern. Mainly be achieved by binary tree Platform: |
Size: 1435648 |
Author:yjt |
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Description: 基于Verilog HDL的视频测试pattern发生器。内置各种常见模式。-Verilog HDL-based video test pattern generator. Built-in a variety of common models. Platform: |
Size: 2048 |
Author: |
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Description: Explanation:- This Program can generate Sine Wave and slide uploaded
image pattern according to sine wave.It is also plot wave
propagation on X-Y coordinates.
This program can save images at the same time to make
pattern sliding videos or can be used for other purpose
System:- Language c++, Opencv Vision Lib. (here OpenCV 2.4.7) Platform: |
Size: 14147584 |
Author:sushichan |
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